The present invention relates to a frequency discriminating circuit for determining whether the frequency of an input signal is higher or lower than a predetermined value.
In general, the engine speed of a vehicle, such as an automotive vehicle varies between 600 r.p.m. (when idling) and 6,000 r.p.m. (in high speed running).
Thus by sensing an electric signal having a frequency from 10 Hz to 100 Hz, it is possible to determine the rotational speed of the engine.
For example, in a device for controlling the number of cylinders supplied with fuel, a decrease in the engine speed during a split-cylinder mode of operation where some of the cylinders are not supplied with fuel is detected to return the engine to its full-cylinder mode of operation.
A conventional circuit, having a simple structure, for determining whether the frequency of an input signal in the range of frequencies mentioned above is higher or lower than a predetermined value is shown in FIG. 1. The circuit comprises a frequency-to-voltage converter (f/v converter) 1 and a comparator 2.
The f/v converter 1 includes a capacitor 3 and a resistor 4, connected in parallel, of which the one junction is connected to a voltage +V of a power supply while the other junction is connected to an input terminal 1a through a diode 5 whose polarity is shown in the drawing.
At the output terminal 1b, a voltage appears, corresponding to a frequency of an input signal applied to the input terminal 1a. Reference numeral 2 denotes a comparator wherein the inverting input terminal (-) is connected to the output terminal 1b while the non-inverting input terminal (+) is connected to the junction between resistors 6 and 7. The comparator 2 compares the output voltage E appearing at the output terminal 1b with a constant reference voltage V.sub.0 obtained from division of the voltage +V by the resistors 6 and 7 to produce an output signal which is high when the output voltage E is below the reference voltage V.sub.0.
The operation of the circuit shown in FIG. 1 will be described with reference to FIG. 2.
Suppose that the pulse signal shown in FIG. 2(a) is applied to the input terminal 1a. When the voltage at the input terminal 1a changes from the voltage +V to zero, the voltage E at the output terminal 1b becomes zero, because, assuming that the resistance of the diode 5 is zero, the capacitor 3 is charged by a current flowing through the diode 5.
Next if the voltage at the input terminal 1a returns to +V, the voltage E at the output terminal 1b does not immediately return to +V because the diode 5 is cut off. Instead, therefore, the capacitor 3 and the resistor 4 form an R-C network, and the capacitor 3 discharges through the resistor 4, so that the output voltage E finally reaches substantially +V.
However, since the output voltage E is returned to zero by the next pulse, the peak value of the output voltage is determined by the width of the +V pulse; the wider the pulse, and thus the lower the frequency of the input signal, the higher the peak value.
Suppose, without loss of generality, that the width of the zero voltage pulses in the input signal can be neglected. The output signal E will reach the reference voltage V.sub.0 a time T.sub.0 after returning to zero, where the relation between T.sub.0 and V.sub.0 is determined by the time constant of the R-C network formed by the capacitor 3 and resistor 4.
Accordingly, if and only if the period of the input signal exceeds T.sub.0, the output of the comparator (shown by (c) in FIG. 2) will contain zero volt pulses. Therefore by detecting these zero volt pulses it is possible to determine whether the input signal is above or below the predetermined frequency corresponding to T.sub.0.
This circuit thus far described has, however, a disadvantage in so far as it is inconvenient to have to determine the state of the output signal by checking for zero volt pulses. It is preferable, and may often be essential to have an output signal which is maintained at zero throughout the period in which the frequency of the input signal is below the predetermined value. For this purpose integrating circuits and so forth may be incorporated into the circuit, but this leads to complications, and the response of the circuit is impaired.
In order to eliminate this problem, another frequency discriminating circuit has been proposed which comprises a f/v converter 11 and a comparator 12, as shown in FIG. 3. In this circuit, the f/v converter 11 further comprises a series circuit comprising a diode 9 and a resistor 8 connected between the power supply +V and the cathode of a diode 5, and a capacitor 10 smaller in capacity than the capacitor 3 and connected between the input terminal 1a and the diode 5.
The input/output characteristics of this circuit are as follows.
Suppose that the capacity of the capacitor 3 is C.sub.1 and that of the capacitor 10 is C.sub.2 (C.sub.2 &lt;C.sub.1) in the circuit 11. Further suppose that the pulses shown in FIG. 2(a) are applied to the input terminal 1a. When the voltage at the input terminal 1a is changed from +V to zero by one of those pulses, the capacitors 3 and 10 are charged by an electric current flowing from the power supply +V to the input terminal 1a through the capacitor 3, the diode 5 and the capacitor 10. As a result, the voltage E at the output terminal 1b lowers from V.sub.1 to V.sub.2 where V.sub.1 denotes the value of the output voltage E just before the pulse was applied thereto (when the voltage at the input terminal 1a was +V).
In the event that there is no charge in the capacitor 3, such as, for example when a first pulse is applied to the input terminal 1a of which voltage is +V, V.sub.1 =+V. On the contrary, in the event that the following pulse is applied to the input terminal 1a before the capacitor 3 is completely discharged after the application of the first pulse, the voltage V.sub.1 =+V-Q/C.sub.1 &lt;+V because of the electric charge Q remaining in the capacitor 3.
If we let V.sub.2 represent the voltage at the output terminal when the voltage at the input terminal 1a has just fallen from V to zero, then ##EQU1##
If the voltage at the input terminal 1a returns from zero to +V, the capacitor 10 discharges through the resistor 8 and the diode 9. Also, the capacitor 3 discharges through the resistor 4 as is the case with FIG. 1. Since the capacity C.sub.2 of the capacitor 10 is smaller than the that C.sub.1 of the capacitor 3, the capacitor 10 discharges more rapidly than the capacitor 3.
Due to the discharging of the capacitor 3, the voltage E at the output terminal 1b gradually increases, with the wave form shown in FIG. 4. Here, E=V.sub.1 denotes the voltage at the output terminal 1b when the voltage at the input terminal 1a is +V and E=V.sub.2 denotes the voltage at the output terminal 1b, which is proportional to the voltage V.sub.1 and which is lower than the voltage V.sub.1 when the output voltage E is held low by an input pulse.
Suppose that when a pulse is applied to the input terminal 1a, the output voltage E is lowered to the voltage V.sub.2 =E.sub.0. When the voltage at the input terminal 1a returns to +V, the output voltage E gradually rises from V.sub.1 =E.sub.0. When the following pulse is applied after a time T.sub.0, the voltage E lowers from the voltage V.sub.1 =E.sub.1 to V.sub.2 =E.sub.2. Thereafter, when the voltage at the input terminal 1a returns to +V, the voltage E gradually increases from V.sub.1 =E.sub.2. When another pulse is applied to the input terminal 1a after the same period of T.sub.0, the output voltage lowers from the voltage V.sub.1 =E.sub.3 to V.sub.2 =E.sub.4.
If a further pulse is applied to the input terminal 1a after a longer period t.sub.1 (when the period T of the input signal is increased), the voltage E lowers from V.sub.1 =E.sub.3 '(&gt;E.sub.3) to V.sub.2 =E.sub.4 '(&gt;E.sub.4). Accordingly, as clearly shown in FIG. 4, a characteristic is that according as the period T of the input signal increases, the peak values V.sub.1 and V.sub.2 of the output voltage E when the pulse is applied gradually increases.
In FIG. 4, even when the period T of the input signal does not vary from t.sub.0, the peak values V.sub.1 and V.sub.2 of the voltage E increase. If the period T remains thereafter at t.sub.0, the increments of the peak values V.sub.1 and V.sub.2 decreases. As a result, the output voltages becomes stable. When the period T is shorter than the stable value t.sub.0 the peak values V.sub.1 and V.sub.2 of the voltage E decrease according to a change in the period.
Thus, the output voltage E of the f/v converter 11 takes the peak values V.sub.1 and V.sub.2 in accordance with the period of the input signal. These peak values are determined in accordance with the preceding peak voltages. For example, in FIG. 4, the voltage V.sub.1 =E.sub.3 is determined in accordance with the period t.sub.0 and V.sub.1 =E.sub.2. Since the voltage V.sub.1 =E.sub.2 is determined by the voltage V.sub.1 =E.sub.1, the peak voltage V.sub.1 =E.sub.3, corresponding to the period t.sub.0, is determined in accordance with the preceding peak voltage V.sub.1 =E.sub.1.
Referring to FIG. 5, when the pulse signal shown in FIG. 5(a) is applied to the input terminal 1a, the output voltage E will continue to oscillate between the upper and lower peak voltages V.sub.0 and V.sub.0 ' as shown in FIG. 5(b), if the period is T.sub.0.
If the pulse has a period T larger than T.sub.0, the voltage E will exceed the voltage V.sub.0. Accordingly, if the voltage V.sub.0 is taken as a reference voltage for the comparator 12, the output voltage of the comparator 12 lowers as shown in FIG. 5(c). Thus, it is determined that the period has increased. It will be noted that, when the pulse has a larger period than T.sub.0, the upper and lower peak voltages are raised as shown in FIG. 5(b).
After sensing this, if the reference voltage remains constant at V.sub.0, the output voltage E appearing when a pulse is applied goes below the voltage V.sub.0. Accordingly, in the FIG. 3 circuit, the output of the comparator 12 is applied through a resistor 13 to the reference input terminal (+) to lower the reference voltage to V.sub.0 ', whereby the output of the comparator 12 does not change even if the output voltage E of the f/v converter lowers. When the period of the input signal returns to T.sub.0, the troughs in the output voltage E lowers at its lower limit to V.sub.0 '. As a result, the output of the comparator 12 returns to the initial high level.
Accordingly, with the frequency discriminating circuit shown in FIG. 3, it is possible to stably detect that the period of the input signal is longer than the predetermined value T.sub.0, that is, that the frequency is lower than the predetermined value. Thus, although it is possible to solve the problem encountered with the circuit shown in FIG. 1, the following problem still remains.
In the FIG. 3 circuit, suppose that the period corresponding to the predetermined frequency is T.sub.0 and the reference voltage of the comparator 12 is V.sub.0. When the period T of the input signal varies slightly in the vicinity of the period T.sub.0, such as, for example, as shown in FIG. 5, when the period T changes from a value slightly shorter than T.sub.0 to a value slightly longer than T.sub.0, it is possible to sense the change in the period T without any substantial delay.
On the other hand, as shown in FIG. 6(a), when the period of the input signal varies greatly from a value T.sub.1 shorter than the period T.sub.0 to a value T longer than the period T.sub.0, it takes a considerable time until the output voltage E exceeds the reference voltage V.sub.0, with the result that there occurs a response delay, as shown in FIG. 6(b).
The response delay time t is long when the period is short and then suddenly varies. As a result, within the predetermined frequency range, the above response delay is a serious problem, when there is a need to detect a lowering of the frequency (increase in the period).